(a) Technical Field
The present invention relates to a method for fabricating a semiconductor device and, in particular, to a process for forming trenches with different depths in cell and boundary regions so as to reduce SAS (self-aligned source) resistance at the cell region.
(b) Description of Related Art
Recently, with the wide applications of flash memories and growing competition in prices thereof, various technologies have been developed to reduce the sizes of the memory devices. One such technology is a self-aligned source (SAS) technique.
The SAS technique is a method for reducing the cell size in a bit line direction and was described in U.S. Pat. Nos. 5,120,671 and 5,103,274. The SAS technique is essentially adopted for below-0.25 μm line width technology. Because the SAS technology can reduce a gap between the gate and the source of a transistor, the size of a memory cell can be reduced by about 20% with the introduction of the SAS technique.
However, the conventional SAS technique has a drawback in that junction resistance of the source per cell dramatically increases because the SAS region is formed along a trench profile.
Moreover, the SAS technique has another drawback in that the actual resistivity at a sidewall of a trench, which is a boundary region between the trench region and an active region, is much greater than and may be about 10 times as much as that at the horizontal surfaces of the trench and active regions, because the depth and amount of the implantation of the injected impurity ions in the sidewall are smaller than those in the other regions, such as the horizontal surfaces of the trench and the active regions.